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| HM538253B Series HM538254B Series 262,144-word x 8-bit Multiport CMOS Video RAM Description The HM538253B/HM538254B is a 2-Mbit multiport video RAM equipped with a 256-kword x 8-bit dynamic RAM and a 512-word x 8-bit SAM (full-sized SAM). Its RAM and SAM operate independently and asynchronously. The HM538253B/HM538254B is upwardly compatible with the HM534253B/HM538123B except that the pseudo-write-transfer cycle is replaced with masked-write-transfer cycle, which has been approved by JEDEC. Furthermore, several new features have been added to the HM538253B/HM538254B which do not conflict with the conventional features. The stopping column feature realizes allows greater flexibility for split SAM register lengths. Persistent mask is also installed according to the TMS34020 features. The HM538254B has Hyper page mode which enables fast page cycle. Features * Multiport organization:RAM and SAM can operate asynchronously and simultaneously: RAM: 256-kword x 8-bit SAM: 512-word x 8-bit * Access time RAM: 70 ns/80 ns/100 ns max SAM: 20 ns/23 ns/25 ns max * Cycle time RAM: 130 ns/150 ns/180 ns min SAM: 25 ns/28 ns/30 ns min * Low power Active RAM: 605 mW/550 mW/495 mW SAM: 358 mW/330 mW/303 mW Standby 38.5 mW max * Masked-write-transfer cycle capability * Stopping column feature capability * Persistent mask capability HM538253B/HM538254B Series * Fast page mode capability (HM538253B) Cycle time: 45 ns/50 ns/55 ns Power RAM: 605 mW/578 mW/550 mW * Hyper page mode capability (HM538254B) Cycle time: 35 ns/40 ns/45 ns Power RAM: 715 mW/660 mW/605 mW * Mask write mode capability * Bidirectional data transfer cycle between RAM and SAM capability * Split transfer cycle capability * Block write mode capability * Flash write mode capability * 3 variations of refresh (8 ms/512 cycles) RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible Ordering Information Type No. HM538253BJ-7 HM538253BJ-8 HM538253BJ-10 HM538254BJ-7 HM538254BJ-8 HM538254BJ-10 HM538253BTT-7 HM538253BTT-8 HM538253BTT-10 HM538254BTT-7 HM538254BTT-8 HM538254BTT-10 Access Time 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 44-pin thin small outline package (TTP-44/40DA) Package 400-mil, 40-pin plastic SOJ (CP-40D) 2 HM538253B/HM538254B Series Pin Arrangement HM538253BJ Series HM538254BJ Series VCC SC SI/O0 SI/O1 SI/O2 SI/O3 DT/OE I/O0 I/O1 I/O2 I/O3 VSS WE RAS A8 A7 A6 A5 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (Top view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 V SS SI/O7 SI/O6 SI/O5 SI/O4 SE I/O7 I/O6 I/O5 I/O4 VSS DSF1 NC CAS QSF A0 A1 A2 A3 V SS VCC SC SI/O0 SI/O1 SI/O2 SI/O3 DT/OE I/O0 I/O1 I/O2 NL NL I/O3 VSS WE RAS A8 A7 A6 A5 A4 VCC HM538253BTT Series HM538254BTT Series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 V SS SI/O7 SI/O6 SI/O5 SI/O4 SE I/O7 I/O6 I/O5 I/O4 NL NL VSS DSF1 NC CAS QSF A0 A1 A2 A3 V SS 3 HM538253B/HM538254B Series Pin Description Pin Name A0-A8 I/O0-I/O7 SI/O0-SI/O7 RAS CAS WE DT/OE SC SE DSF1 QSF VCC VSS NL NC Function Address inputs RAM port data inputs/outputs SAM port data inputs/outputs Row address strobe Column address strobe Write enable Data transfer/output enable Serial clock SAM port enable Special function input flag Special function output flag Power supply Ground No lead No connection 4 HM538253B/HM538254B Series Block Diagram A0 - A8 A0 - A8 Column Address Buffer A0 - A8 Row Address Buffer Refresh Counter Row Decoder Sense Amplifier & I/O Bus Block Write Flash Write Control Control 0 511 Memory Array Serial Address Counter SAM Column Decoder QSF 511 Column Decoder Transfer Gate Data Register 0 Input Data Control Address Mask Register Transfer Gate Data Register Serial Output Buffer SAM I/O Bus Serial Input Buffer Mask Register Color Resister SI/O0 - SI/O7 Input Buffer Output Buffer Timing Generator I/O0 - I/O7 RAS CAS DT/OE WE DSF1 SC SE 5 HM538253B/HM538254B Series Pin Functions RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of R A S. The input level of these signals determines the operation cycle of the HM538253B/HM538254B. CAS (input pin): Column address and DSF1 signals are fetched into the chip at the falling edge of CAS, which determines the operation mode of the HM538253B/HM538254B. A0-A8 (input pins): Row address (AX0-AX8) is determined by A0-A8 level at the falling edge of RAS. Column address (AY0-AY8) is determined by A0-A8 level at the falling edge of CAS. In transfer cycles, row address is the address on the word line which transfers data with the SAM data register, and column address is the SAM start address after transfer. WE: The WE pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge of RAS, the HM538253B/ HM538254B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. (WE level at the falling edge of RAS is don't care in read cycle.) When WE is high at the falling edge of R A S, a no mask write cycle is executed. After that, WE switches to read/write cycles. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of RAS. When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is high, data is transferred from RAM to SAM (data is read from RAM). I/O0-I/O7 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins is masked and internal data is retained. After that, they function as input/output pins as those of a standard DRAM. In block write cycle, the data functions as column mask data at the falling edges of CAS and WE. DT/OE (input pin): The DT/OE pin functions as a DT (data transfer) pin at the falling edge of RAS and as an OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because the internal pointer is incremented at the rising edge of SC. SI/O0-SI/O7 (input/output pins): SI/Os are SAM input/output pins. I/O direction is determined by the previous transfer cycle. If it was a read transfer cycle, SI/O outputs data. If it was a masked write transfer cycle, SI/O inputs data. DSF1 (input pin): DSF1 is a special function data input flag pin. It is set to high at the falling edge of RAS when new functions such as color register and mask register read/write, split transfer, and flash write, are used. 6 HM538253B/HM538254B Series DSF2 (input pin): DSF2 is also a special function data input flag pin. This pin is fixed to low level in all operations of the HM538253B/HM538254B. QSF (output pin): QSF outputs data of address A8 in SAM. QSF is switched from low to high by accessing address 255 in SAM, and from high to low by accessing address 511 in SAM. Table 1 Operation Cycles of the HM538253B/HM538254B RAS Mnemonic Code CBRS CBRR CBRN MWT MSWT RT SRT RWM BWM RW (No) BW (No) FWM CAS Address CAS -- -- -- TAP TAP TAP TAP I/On Input RAS -- -- -- WM WM -- -- CAS/WE -- -- -- -- -- -- -- Input data Column Mask Input Data Column Mask -- Mask Data Color -- CAS DT/OE WE DSF1 DSF2 DSF1 DSF2 RAS 0 0 0 1 1 1 1 1 1 1 1 1 -- -- -- 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 1 0 1 -- 0 1 -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Stop -- -- Row Row Row Row Row Row Row Row Row (Row) (Row) Mode Column WM Column WM Column -- Column -- -- -- -- -- WM -- -- Data LMR and 1 Old Mask Set LCR Option 1 0 7 HM538253B/HM538254B Series Table 1 Operation Cycles of the HM538253B/HM538254B (cont) Register Mnemonic Code CBRS CBRR CBRN MWT MSWT RT SRT RWM BWM RW (no) BW (no) FWM LMR and Old Mask Set LCR Option Write Mask -- -- -- Yes Yes -- -- Yes Yes No No Yes -- -- -- Pers W.M. -- Reset -- No Yes No Yes -- -- No Yes No Yes No No No Yes Set -- -- WM -- Reset -- Load/use Use Load/use Use -- -- Load/use Use Load/use Use -- -- Load/use Use Load -- -- -- Use Use -- Load -- Color -- -- -- -- -- -- -- -- No. Of Bndry Set Reset -- -- Use -- Use -- -- -- -- -- -- -- -- Function CBR refresh with stop register set CBR refresh with register reset CBR refresh (no reset) Masked write transfer (new/old mask) Masked split write transfer (new/old mask) Read transfer Split read transfer Read/write (new/old mask) Block write (new/old mask) Read/write (no mask) Block write (no mask) Masked flash write (new/old mask) Load mask register and old mask set Load color resister set Notes: 1. With CBRS, all SAM operations use stop register. 2. After LMR, RWM, BWM, FWM, MWT, and MSWT, use old mask which can be reset by CBRR 3. DSF2 is fixed low in all operation (for the addition of operation modes in future). Operation of HM538253B/HM538254B RAM Port Operation RAM Read Cycle (DT/OE high, CAS high and DSF1 low at the falling edge of RAS, DSF1 low at the falling edge of CAS: Mnemonic Code; R) Row address is entered at the RAS falling edge and column address at the C AS falling edge to the device as in standard DRAM operation. Then, when WE is high and DT/OE is low while C AS is low, the selected address data outputs through the I/O pin. At the falling edge of RAS , DT/OE and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address access time (tAA) and RAS to column address delay time (tRAD ) specifications are added to enable fast page mode/hyper page mode. 8 HM538253B/HM538254B Series RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write)(DT/OE high, CAS high and DSF1 are low at the falling edge of R AS, and DSF1 is low at the falling edge of CAS): Mnemonic Code; W No Mask Write Cycle (WE high at the falling edge of RAS): When CAS is set low and WE is set low after RAS low, a write cycle is executed. If WE is set low before the CAS falling edge, this cycle becomes an early write cycle and all I/O become in high impedance. If WE is set low after the CAS falling edge, this cycle becomes a delayed write cycle. I/O does not become high impedance in this cycle, so data should be entered with OE in high. If W E is set low after tC W D (min) and tAWD (min) after the CAS falling edge, this cycle becomes a read-modify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O contention, data should be input after reading data and driving OE high. Mask Write Mode (WE low at the falling edge of RAS):If WE is set low at the falling edge of RAS, two modes of mask write cycle are possible. In new mask mode, mask data is loaded from I/O pin and used. Whether or not an I/O is written depends on I/O level at the falling edge of RAS. The data is written in high level I/Os, and the data is masked and retained in low level I/Os. This mask data is effective during the RAS cycle. So, in page mode cycles the mask data is retained during the page access. If a load mask register cycle (LMR) has been performed, Mask write cycle (RAM write cycle, flash write cycle, block write cycle, masked write transfer cycle and masked sprit write transfer cycle) becomes all persistent mask mode. The mask data is not loaded from I/O pins and the mask data stored in mask registers persistently are used. This operation known as persistent write mask is reset by CBRR cycle, and become a new mask. Fast Page Mode Cycle (HM538253B) (DT/OE high, CAS high and DSF1 low at the falling edge of RAS): Fast page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and block write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time (tRAD), and access time from CAS precharge (t ACP ) are added. In one RAS cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 s). Hyper Page Mode Cycle (HM538254B) (DT/OE high, CAS high and DSF1 low at the falling edge of RAS): Hyper page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one forth of the random read/write cycle. In this cycle, read, write, and block write cycles can be mixed. Note that address access time (t AA ), RAS to column address delay time (tRAD), and access time from CAS precharge (t ACP ) are added. column address is latched by CAS low edge triger, access time from CAS is determined by tCAC (tAA from column address, t ACP from CAS high edge). Dout data is held during CAS high and is sustained until next Dout. Data output enable/disable is controlled by DT/OE and when both RAS and CAS become high, Data output become High-Z. In one RAS cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 s). Color Register Set/Read Cycle (CAS high, DT/OE high, W E high and DSF1 high at the falling edge of RAS: Mnemonic Code; LCR) In color register set cycle, color data is set to the internal color register used in flash write cycle or block write cycle. 8 bits of internal color register are provided at each I/O. This register is composed of static circuits, so once it is set, it retains the data until reset. Since color register set cycle is the 9 HM538253B/HM538254B Series same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. In this cycle, the HM538253B/ HM538254B refreshes the row address fetched at the falling edge of RAS. Mask Register Set/Read Cycle (CAS high, DT/OE high, WE high, and DSF1 low at the falling edge of R AS: Mnemonic Code; LMR) In this cycle, mask data is set to the internal mask register persistently used in mask write cycle, block write cycle, flash write cycle, masked write transfer, and masked split write transfer. 8 bits of internal mask register are provided at each I/O. This mask register is composed of static circuits. So once it is reset by CBRR cycle, it retains the data until reset or reselect. Once LMR is set, mask write cycle data is written by persistent mask data. Since mask register set cycle is just the same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. Flash Write Cycle (CAS high, D T/OE high, W E low, and DSF1 high at the falling edge of R A S: Mnemonic; FW) In a flash write cycle, a row of data (512 word x 8 bit) is cleared to 0 or 1 at each I/O according to the data in the color register mentioned before. It is also necessary to mask I/O in this cycle. When CAS and DT/OE is set high, WE is low, and DSF1 is high at the falling edge of RAS, this cycle starts. Then, the row address to clear is given to row address. Mask data is the same as that of a RAM write cycle. Cycle time is the same as those of RAM read/write cycles, so all bits can be cleared in 1/512 of the usual cycle time. (See figure 1.) Block Write Cycle (CAS high, DT/OE high and DSF1 low at the falling edge of RAS, DSF1 high and WE low at the falling edge of CAS: Mnemonic; BW) In a block write cycle, 4 columns of data (4 column x 8 bit) are cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are disregarded. The mask data on I/Os and the mask data on column address can be determined independently. I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) The block write cycle is as the same as the usual write cycle, so early and delayed write, read-modify-write, and page mode write cycle can be executed. No Mask Mode Block Write Cycle (WE high at the falling edge of RAS): The data on 8 I/Os are all cleared when WE is high at the falling edge of RAS. Mask Block Write Cycle (WE low at the falling edge of RAS):When WE is low at the falling edge of RAS, the HM538253B/HM538254B starts mask block write cycle to clear the data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. In new mask mode, the mask data is available in the RAS cycle. In persistent mask mode, I/O don't care about mask mode. 10 HM538253B/HM538254B Series Color Register Set Cycle RAS CAS Address WE DT/OE DSF1 I/O Color Data Set color register *1 *1 Execute flash write into each I/O on row address Xi using color register. Execute flash write into each I/O on row address Xj using color register. Row Xi Xj Flash Write Cycle Flash Write Cycle Note: 1. I/O Mask Data (In new mask mode) Low: Mask High: Non Mask In persistent mask mode, I/O don't care Figure 1 Use of Flash Write 11 HM538253B/HM538254B Series Color Register Set Cycle RAS CAS Address WE DT/OE DSF1 I/O *1 WE Low Mode New mask mode Persistent mask mode No mask I/O data/RAS Mask H or L (mask register used) H or L Color Data *1 Column Mask Block Write Cycle Block Write Cycle Row Row *1 Column A2-A8 Row *1 Column A2-A8 *1 Column Mask High I/O Mask Data (In new mask mode) Low: Mask High: Non Mask In persistent mask mode, I/O H or L Column Mask Data I/O0 I/O1 I/O2 I/O3 Column0 (A0 = 0, A1 = 0) Mask Data Column1 (A0 = 1, A1 = 0) Mask Data Column2 (A0 = 0, A1 = 1) Mask Data Column3 (A0 = 1, A1 = 1) Mask Data Low: Mask High: Non Mask Figure 2 Use of Block Write Transfer Operation The HM538253B/HM538254B provides the read transfer cycle, split read transfer cycle, masked write transfer cycle and masked split write transfer cycle as data transfer cycles. These transfer cycles are set by driving CAS high and DT/OE low at the falling edge of RAS. They have following functions: * Transfer data between row address and SAM data register Read transfer cycle and split read transfer cycle: RAM to SAM Masked write transfer cycle and masked split write transfer cycle: SAM to RAM * Determine SI/O state (except for split read transfer and masked split write transfer cycle) Read transfer cycle: SI/O output Masked write transfer cycle: SI/O input 12 HM538253B/HM538254B Series * Determine first SAM address to access after transferring at column address (SAM start address). SAM start address must be determined by read transfer cycle or masked write transfer cycle (split transfer cycle isn't available) before SAM access, after power on, and determined for each transfer cycle. * Use the stopping columns (boundaries) in the serial shift register. If the stopping columns have been set, split transfer cycles use the stopping columns, but any boundaries cannot be set as the start address. * Load/use mask data in masked write transfer cycle and masked split write transfer cycle. Read Transfer Cycle (CAS high, D T/OE low, W E high and DSF1 low at the falling edge of R A S): Mnemonic; RT This cycle becomes read transfer cycle by driving DT/OE low, WE high and DSF1 low at the falling edge of RAS. The row address data (512 x 8 bits) determined by this cycle is transferred to SAM data register synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs from SAM start address determined by column address. In read transfer cycle, DT/OE must rise to transfer data from RAM to SAM. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min) specified between the last SAM access before transfer and DT/OE rising edge and t SDH (min) specified between the first SAM access and DT/OE rising edge must be satisfied. (See figure 3.) RAS CAS Address DT/OE DSF1 SC SI/O SAM Data before Transfer Yj Yj + 1 L Xi Yj t SDD t SDH SAM Data after Transfer Figure 3 Real Time Read Transfer When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high impedance before t SZS (min) of the first SAM access to avoid data contention. Masked Write Transfer cycle (CAS high, DT/OE low, WE low, and DSF1 low at the falling edge of RAS): Masked write transfer cycle can transfer only selected I/O data in a row of data input by serial write cycle to 13 HM538253B/HM538254B Series RAM. Whether I/O data is transferred or not depends on the corresponding I/O level (mask data) at the falling edge of RAS. This mask transfer operation is the same as a mask write operation in RAM cycles, so the persistent mode can be supported. The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after t SRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this period, SC must not be risen. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by write transfer cycle. However, the address to write data must be the same as that of the read transfer cycle or the split read transfer cycle (row address AX8). Figure 4 shows the example of row bit data transfer. In case AX8 is 0, data cannot be transferred RAM address within the range of 100000000 to 111111111. Same as the case of AX8 = 1. (Row address) A8 ........ A0 000000000 011111111 100000000 SAM ........ RAM (Row address) A8 ........A0 000000000 011111111 100000000 SAM Possible RAM Impossible RAM RAM 111111111 SAM (Read transfer cycle) (Write transfer cycle) 111111111 SAM Figure 4 Example of Row Bit Data Transfer Split Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF1 high at the falling edge of RAS): To execute a continuous serial read by real-time read transfer, the HM538253B/HM538254B must satisfy SC and DT/OE timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it possible to execute a continuous serial read without the above timing limitation. The HM538253B/HM538254B supports two types of split register operation. One is the normal split register operation to split the data register into two halves. The other is the boundary split register operation using stopping columns described later. Figure 5 shows the block diagram for the normal split register operation. SAMdata register (DR) consists of 2 split buffers, whose organizations are 256-word x 8-bit each. Suppose that data is read from upper data register DR1. (The row address AX8 is 0 and SAM address A8 is 1.) When split read transfer is executed setting row address AX8 to 0 and SAM start addresses A0 to A7, 256-word x 8-bit data is transferred from RAM to the lower data register DR0 (SAM address A8 is 0) automatically. After data is read from data register DR1, data read begins from SAM start addresses of data register DR0. If the next split read transfer isn't executed while data is read from data register DR0, data read begins from SAM start address 0 of DR1 14 HM538253B/HM538254B Series after data is read from data register DR0. If split read transfer is executed setting row address AX8 to 1 and SAM start addresses A0 to A7 while data is read from data register DR1, 256-word x 8-bit data is transferred to data register DR2. After data is read from data register DR1, data read begins from the SAM start addresses of data register DR2. If the next split read transfer isn't executed while data is read from data register DR2, data read begins from SAM start address 0 of data register DR1 after data is read from data register DR2. In split read data transfer, the SAM start address A8 is automatically set in the data register, which isn't used. The data on SAM address A8, which will be accessed next, outputs to QSF. QSF is switched from low to high by accessing SAM last address 255 and from high to low by accessing address 511. SAM Column Decoder DR1 SAM I/O Bus AX8 = 0 DR0 SAM I/O Bus Memory Array DR3 Memory Array AX8 = 1 SAM I/O Buffer SI/O Figure 5 Split Transfer Block Diagram Split read transfer cycle is set when CAS is high, DT/OE is low, WE is high and DSF1 is high at the falling edge of RAS. The cycle can be executed asyncronously with SC. However, HM538253B/ HM538254B must be satisfied t STS (min) timing specified between SC rising (boundary address) and RAS falling. In split transfer cycle, the HM538253B/HM538254B must satisfy tRST (min), tCST (min) and tAST(min) timings specified between RAS or CAS falling and column address. (See figure 6.) In split read transfer, SI/O isn't switched to output state. Therefore, read transfer must be executed to switch SI/O to output state when the previous transfer cycle is masked write transfer cycle or masked split write transfer cycle. Masked Split Write Transfer Cycle (CAS high, DT/OE low, WE low and DSF1 high at the falling edge of RAS): A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in write transfer. Masked split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST (min) and tAST (min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input state in this cycle. If SI/O is in output state, masked write transfer cycle should be executed to DR2 15 HM538253B/HM538254B Series switch SI/O into input state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by masked split write transfer cycle. However masked write transfer cycle must be executed before masked split write transfer cycle. And in this masked split write transfer cycle, the MSB of row address (AX8) to write data must be the same as that of the read transfer cycle or the split read transfer cycle. In this cycle, the boundary split register operation using stopping columns is possible as with split read transfer cycle. RAS tSTS (min) CAS t CST (min) Address Xi t AST (min) DT/OE DSF1 SC Bi Ym Yj tRST (min) Bj - 1 Bj Yj Note: Ym is the SAM start address in before SRT. Bi and Bj initiate the boundary address. Figure 6 Split Transfer Limitation Table 2 Stopping Column Boundary Table Stop Address Boundary Code Column Size B2 B3 B4 B5 B6 B7 B8 4 8 16 32 64 128 256 A2 0 1 1 1 1 1 1 A3 x 0 1 1 1 1 1 A4 x x 0 1 1 1 1 A5 x x x 0 1 1 1 A6 x x x x 0 1 1 A7 x x x x x 0 1 Notes: 1. A0, A1, and A8: H or L 2. x: H or L 16 HM538253B/HM538254B Series Stopping Column in Split Transfer Cycle: The HM538253B/HM538254B has the boundary split register operation using stopping columns. If a CBRS cycle has been performed, split transfer cycle performs the boundary operation. Figure 7 shows an example of boundary split register. (Boundary code is B7.) First a read data transfer cycle is executed, and SAM start addresses A0 to A8 are set. The RAM data is transferred to the SAM, and SAM serial read starts from the start address (Y1) on the lower SAM. After that, a split read transfer cycle is executed, and the next start address (Y2) is set. The RAM data is transferred to the upper SAM. When the serial read arrive at the first boundary after the split read transfer cycle, the next read jumps to the start address (Y2) on the upper SAM (jump 1) and continues. Then the second split read transfer cycle is executed, and another start address (Y3) is set. The RAM data is transferred to the lower SAM. When the serial read arrive at the other boundary again, the next read jumps to the start address (Y3) on the lower SAM. In stopping column, split transfer is needed for jump operation between lower SAM and upper SAM. Stopping Column Set Cycle (CBRS): Start a stopping column set cycle by driving CAS low, WE low, and DSF1 high at the falling edge of R AS. Stopping column data (boundaries) are latched from address inputs on the falling edge of RAS. To determine the boundary, A2 to A7 can be used, and A0, A1, and A8 don't care. In the HM538253B/HM538254B, 7 types of boundary (B2 to B8) can be set including the default case. (See stopping column boundary table.) If A2 to A6 are set high and A7 is set low, the boundaries (B7) are selected. Figure 6 shows the example. Once a CBRS is executed, next sprit transfer cycle data become stopping columm data. Stopping columm is reset by CBBR. Column size 128 bit Boundaries (B7) (Y1) (Y3) (Y2) Start Jump 1 Lower SAM 256 bit Jump 2 Upper SAM 256 bit Figure 7 Example of Boundary Split Register Register Reset Cycle (CBRR): Start a register reset cycle (CBRR) by driving CAS low, W E high, and DSF1 low at the falling edge of R AS. A CBRR can reset the persistent mask operation and stopping column operation, so the HM538253B/HM538254B becomes the new mask operation and boundary code B8. When a CBRR is executed for stopping column operation reset and split transfer operation, it needs to satisfy t STS (min) and tRST (min) between RAS falling and SC rising. 17 HM538253B/HM538254B Series No Reset CBR cycle (CBRN): This cycle becomes no reset CBR cycle (CBRN) by driving CAS low, WE high and DSF1 high at the falling edge of RAS. The CBRN can only execute the refresh operation. SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is a read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Serial Write Cycle If the previous data transfer cycle is a masked write transfer cycle, SAM port goes into write mode. In this cycle, SI/O data is fetched into the data register at the SC rising edge like in the serial read cycle. If SE is high, SI/O data isn't fetched into the data register. The internal pointer is incremented by the SC rising, so SE high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Refresh RAM Refresh RAM, which is composed of dynamic circuits, requires refresh cycles to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2) CAS-before-R AS (CBRN, CBRS, and CBRR) refresh cycle, and (3) Hidden refresh cycle. The cycles which activate RAS, such as read/write cycles or transfer cycles, can also refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. RAS-Only Refresh Cycle: R AS-only refresh cycle is executed by activating only the RAS cycle with C AS fixed high after inputting the row address (refresh address) from external circuits. To distinguish this cycle from a data transfer cycle, DT/OE must be high at the falling edge of RAS. CBR Refresh Cycle: CBR refresh cycle (CBRN, CBRS and CBRR) are set by activating CAS before RAS. In this cycle, the refresh address need not be input through external circuits because it is input through an internal refresh counter. In this cycle, output is high impedance and power dissipation is low because CAS circuits are not operating. Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS when DT/OE and CAS keep low in normal RAM read cycles. SAM Refresh SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh. 18 HM538253B/HM538254B Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -0.5 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min 4.5 2.4 -0.5 *2 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Notes 1 1 1 Notes: 1. All voltage referred to VSS 2 -3.0 V for pulse width 10 ns. 19 HM538253B/HM538254B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM538253B/HM538254B -7 Parameter Operating current -8 -10 Max Unit Test Conditions 90 mA RAS, CAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS, CAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS, CAS = VIH SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS cycling CAS = VIH t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min Symbol Min Max Min Max Min I CC1 -- 110 -- 100 -- I CC7 -- 165 -- 150 -- 140 mA Block write current I CC1BW -- 115 -- 105 -- 90 mA I CC7BW -- 170 -- 155 -- 140 mA Standby current I CC2 I CC8 -- -- 7 65 -- -- 7 60 -- -- 7 55 mA mA RAS-only refresh current I CC3 -- 110 -- 100 -- 90 mA I CC9 -- 165 -- 150 -- 135 mA Fast page mode current (HM538253B) *3 I CC4 -- 110 -- 105 -- 100 mA I CC10 -- 160 -- 155 -- 150 mA Fast page mode I CC4BW block write current *3 I CC10BW -- 130 -- 125 -- 120 mA -- 185 -- 175 -- 165 mA 20 HM538253B/HM538254B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont) HM538253B/HM538254B -7 Parameter Hyper page mode current (HM538254B) *3 -8 -10 Max Unit Test Conditions 110 mA CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS, CAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min Symbol Min Max Min Max Min I CC4 -- 130 -- 120 -- I CC10 -- 185 -- 170 -- 160 mA Hyper page mode I CC4BW block write current *3 I CC10BW -- 155 -- 140 -- 130 mA mA 175 175 -- 210 -- 190 -- CAS-before-RAS refresh current I CC5 I CC11 -- -- 85 -- 75 -- 65 mA 140 -- 130 -- 120 mA Data transfer current I CC6 -- 130 -- 115 -- 100 mA I CC12 -- 180 -- 165 -- 145 mA Input leakage current Output leakage current I LI I LO -10 10 -10 10 2.4 -- -- 0.4 -10 10 -10 10 2.4 -- -- 0.4 -10 -10 2.4 -- 10 10 -- 0.4 A A V V I OH = -1 mA I OL = 2.1 mA Output high voltage VOH Output low voltage VOL Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once while RAS is low and CAS is high. 3. Address can be changed once in 1 page cycle (tPC). 21 HM538253B/HM538254B Series Capacitance (Ta = 25C, VCC = 5 V 10%, f = 1 MHz, Bias: Clock, I/O = VCC, Address = VSS) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (I/O, SI/O, QSF) Note: Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 5 7 Unit pF pF pF Note 1 1 1 1. This parameter is sampled and not 100% tested. AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *16 Test Conditions * * * * * Input rise and fall time: 5 ns Input pulse levels: VSS to 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: RAM 1 TTL + CL (50 pF) SAM, QSF 1 TTL + CL (30 pF) (Including scope and jig) 22 HM538253B/HM538254B Series Common Parameter HM538253B/HM538254B -7 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS hold time referred to CAS CAS hold time referred to RAS CAS to RAS precharge time Transition time (rise to fall) Refresh period DT to RAS setup time DT to RAS hold time DSF1 to RAS setup time DSF1 to RAS hold time DSF1 to CAS setup time DSF1 to CAS hold time Data-in to CAS delay time Data-in to OE delay time Output buffer turn-off delay referred to CAS Output buffer turn-off delay referred to OE Symbol Min Max t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RSH t CSH t CRP tT t REF t DTS t DTH t FSR t RFH t FSC t CFH t DZC t DZO t OFF1 t OFF2 130 -- 50 70 20 0 10 0 12 20 20 70 10 3 -- 0 10 0 10 0 12 0 0 -- -- -- 10000 -- -- -- -- -- 50 -- -- -- 50 8 -- -- -- -- -- -- -- -- 15 15 -8 Min Max 150 -- 60 80 20 0 10 0 15 20 20 80 10 3 -- 0 10 0 10 0 15 0 0 -- -- -- 10000 -- -- -- -- -- 60 -- -- -- 50 8 -- -- -- -- -- -- -- -- 20 20 -10 Min Max 180 -- 70 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns 4 4 5 5 3 2 100 10000 25 0 10 0 15 20 25 -- -- -- -- -- 75 -- 100 -- 10 3 -- 0 10 0 10 0 15 0 0 -- -- -- 50 8 -- -- -- -- -- -- -- -- 20 20 23 HM538253B/HM538254B Series Read Cycle (RAM), Page Mode Read Cycle HM538253B/HM538254B -7 Parameter Access time from RAS Access time from CAS Access time from OE Address access time Read command setup time Read command hold time Read command hold time referred to RAS RAS to column address delay time Column address to RAS lead time Column address to CAS lead time Page mode cycle time CAS precharge time Access time from CAS precharge Page mode RAS pulse width Symbol Min Max t RAC t CAC t OAC t AA t RCS t RCH t RRH t RAD t RAL t CAL t PC t CP t ACP t RASP -- -- -- -- 0 0 0 15 35 35 45 7 -- 70 70 20 20 35 -- -- -- 35 -- -- -- -- 40 -8 Min Max -- -- -- -- 0 0 5 15 40 40 50 10 -- 80 20 20 40 -- -- -- 40 -- -- -- -- 45 -10 Min Max -- -- -- -- 0 0 10 15 45 45 55 10 -- 100 25 25 45 -- -- -- 55 -- -- -- -- 50 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 2 6, 7 7, 8 7 7, 9 100000 80 100000 100 100000 ns 24 HM538253B/HM538254B Series Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle HM538253B/HM538254B -7 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time WE to RAS setup time WE to RAS hold time Mask data to RAS setup time Mask data to RAS hold time OE hold time referred to WE Page mode cycle time CAS precharge time CAS to data-in delay time Page mode RAS pulse width Symbol Min Max t WCS t WCH t WP t RWL t CWL t DS t DH t WS t WH t MS t MH t OEH t PC t CP t CDD t RASP 0 12 12 20 20 0 12 0 10 0 10 15 45 7 15 70 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -8 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 50 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -10 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 55 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 12 12 11 100000 80 100000 100 100000 ns 25 HM538253B/HM538254B Series Read-Modify-Write Cycle HM538253B/HM538254B -7 Parameter Read-modify-write cycle time RAS pulse width (read-modify-write cycle) CAS to WE delay time Column address to WE delay time OE to data-in delay time Access time from RAS Access time from CAS Access time from OE Address access time RAS to column address delay time Read command setup time Write command to RAS lead time Write command to CAS lead time Write command pulse width Data-in setup time Data-in hold time OE hold time referred to WE Symbol Min Max t RWC t RWS t CWD t AWD t ODD t RAC t CAC t OAC t AA t RAD t RCS t RWL t CWL t WP t DS t DH t OEH 180 -- 120 10000 40 60 15 -- -- -- -- 15 0 20 20 12 0 12 15 -- -- -- 70 20 20 35 35 -- -- -- -- -- -- -- -8 Min Max 200 -- 130 10000 45 65 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 80 20 20 40 40 -- -- -- -- -- -- -- -10 Min Max 230 -- 150 10000 50 70 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 100 25 25 45 55 -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 14 14 12 6, 7 7, 8 7 7, 9 Refresh Cycle HM538253B/HM538254B -7 Parameter CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS precharge to CAS hold time Symbol Min Max t CSR t CHR t RPC 10 10 10 -- -- -- -8 Min Max 10 10 10 -- -- -- -10 Min Max 10 10 10 -- -- -- Unit Notes ns ns ns 26 HM538253B/HM538254B Series Flash Write Cycle, Block Write Cycle, and Register Read Cycle HM538253B/HM538254B -7 Parameter CAS to data-in delay time OE to data-in delay time Symbol Min Max t CDD t ODD 15 15 -- -- -8 Min Max 20 20 -- -- -10 Min Max 20 20 -- -- Unit Notes ns ns 13 13 CBR Refresh with Register Reset HM538253B/HM538254B -7 Parameter Split transfer setup time Split transfer hold time referred to RAS Symbol Min Max t STS t RST 20 70 -- -- -8 Min Max 20 80 -- -- -10 Min Max 25 -- Unit Notes ns ns 100 -- Hyper Page Mode Cycle (HM538254B) HM538254B -7 Parameter Column address to CAS lead time Hyper page mode cycle time Hyper page CAS precharge time Hyper page data out hold time Data-out buffer turn-off time (RAS) Data-out buffer turn-off time (CAS) RAS to data-in delay time Symbol Min Max t CAL t PC t CP t DOH t RHZ t CHZ t RDD 25 35 5 4 -- -- 20 -- -- -- -- 15 15 -- -8 Min Max 30 40 10 5 -- -- 20 -- -- -- -- 20 20 -- -10 Min Max 35 45 10 5 -- -- 20 -- -- -- -- 20 20 -- Unit Notes ns ns ns ns ns ns ns 5 5 13 27 HM538253B/HM538254B Series Read Transfer Cycle HM538253B/HM538254B -7 Parameter DT hold time referred to RAS DT hold time referred to CAS DT hold time referred to DT precharge time DT to RAS delay time SC to RAS setup time 1st SC to RAS hold time 1st SC to CAS hold time 1st SC to column address hold time Last SC to DT delay time 1st SC to DT hold time DT to QSF delay time QSF hold time referred to DT Serial data-in to 1st SC delay time Serial clock cycle time SC pulse width SC precharge time SC access time Serial data-out hold time Serial data-in setup time Serial data-in hold time RAS to column address delay time Column address to RAS lead time RAS to QSF delay time CAS to QSF delay time QSF hold time referred to RAS QSF hold time referred to CAS Symbol Min Max t RDH t CDH t ADH t DTP t DRD t SRS t SRH t SCH t SAH t SDD t SDH t DQD t DQH t SZS t SCC t SC t SCP t SCA t SOH t SIS t SIH t RAD t RAL t RQD t CQD t RQH t CQH 60 20 25 20 60 15 70 25 40 5 10 -- 5 0 25 5 10 -- 5 0 15 15 35 -- -- 20 5 10000 -- -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- 20 -- -- -- 35 -- 70 35 -- -- -8 Min Max 65 20 30 20 70 20 80 25 45 5 13 -- 5 0 28 10 10 -- 5 0 15 15 40 -- -- 20 5 10000 -- -- -- -- -- -- -- -- -- -- 35 -- -- -- -- -- 23 -- -- -- 40 -- 75 35 -- -- -10 Min Max 80 25 30 30 80 30 10000 -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 15 15 100 -- 25 50 5 15 -- 5 0 30 10 10 -- 5 0 15 15 45 -- -- 25 5 -- -- -- -- 35 -- -- -- -- -- 25 -- -- -- 55 -- 85 35 -- -- 28 HM538253B/HM538254B Series Masked Write Transfer Cycle HM538253B/HM538254B -7 Parameter SC setup time referred to RAS RAS to SC delay time Serial output buffer turn-off time referenced to RAS RAS to serial data-in delay time RAS to QSF delay time CAS to QSF delay time QSF hold time referred to RAS QSF hold time referred to CAS Serial clock cycle time SC pulse width SC precharge time SC access time Serial data-out hold time Serial data-in setup time Serial data-in hold time Symbol Min Max t SRS t SRD t SRZ t SID t RQD t CQD t RQH t CQH t SCC t SC t SCP t SCA t SOH t SIS t SIH 15 20 10 30 -- -- 20 5 25 5 10 -- 5 0 15 -- -- 30 -- 70 35 -- -- -- -- -- 20 -- -- -- -8 Min Max 20 25 10 35 -- -- 20 5 28 10 10 -- 5 0 15 -- -- 35 -- 75 35 -- -- -- -- -- 23 -- -- -- -10 Min Max 30 25 10 50 -- -- 25 5 30 10 10 -- 5 0 15 -- -- 50 -- 85 35 -- -- -- -- -- 25 -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 15 29 HM538253B/HM538254B Series Split Read Transfer Cycle, Masked Split Write Transfer Cycle HM538253B/HM538254B -7 Parameter Split transfer setup time Split transfer hold time referred to RAS Split transfer hold time referred to CAS Split transfer hold time referred to column address SC to QSF delay time QSF hold time referred to SC Serial clock cycle time SC pulse width SC precharge time SC access time Serial data-out hold time Serial data-in setup time Serial data-in hold time RAS to column address delay time Column address to RAS lead time Symbol Min Max t STS t RST t CST t AST t SQD t SQH t SCC t SC t SCP t SCA t SOH t SIS t SIH t RAD t RAL 20 70 20 35 -- 5 25 5 10 -- 5 0 15 15 35 -- -- -- -- 30 -- -- -- -- 20 -- -- -- 35 -- -8 Min Max 20 80 20 40 -- 5 28 10 10 -- 5 0 15 15 40 -- -- -- -- 30 -- -- -- -- 23 -- -- -- 40 -- -10 Min Max 25 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 100 -- 25 45 -- 5 30 10 10 -- 5 0 15 15 45 -- -- 30 -- -- -- -- 25 -- -- -- 55 -- Serial Read Cycle, Serial Write Cycle HM538253B/HM538254B -7 Parameter Serial clock cycle time SC pulse width SC precharge width Access time from SC Access time from SE Serial data-out hold time Symbol Min Max t SCC t SC t SCP t SCA t SEA t SOH 25 5 10 -- -- 5 -- 0 0 -- -- -- 20 17 -- 15 -- -- -8 Min Max 28 10 10 -- -- 5 -- 0 0 -- -- -- 23 20 -- 20 -- -- -10 Min Max 30 10 10 -- -- 5 -- 0 0 -- -- -- 25 25 -- 20 -- -- Unit Notes ns ns ns ns ns ns ns ns ns 5,17 5,17 15 15 Serial output buffer turn-off time referred t SHZ to SE SE to serial output in low-Z Serial data-in setup time t SLZ t SIS 30 HM538253B/HM538254B Series Serial Read Cycle, Serial Write Cycle (cont) HM538253B/HM538254B -7 Parameter Serial data-in hold time Serial write enable setup time Serial wrtie enable hold time Serial write disable setup time Serial write disable hold time Symbol Min Max t SIH t SWS t SWH t SWIS t SWIH 15 0 15 0 15 -- -- -- -- -- -8 Min Max 15 0 15 0 15 -- -- -- -- -- -10 Min Max 15 0 15 0 15 -- -- -- -- -- Unit Notes ns ns ns ns ns Notes: 1. AC measurements assume t T = 5 ns. 2. When t RCD > tRCD (max) and tRAD > tRAD (max), access time is specified by tCAC or tAA. 3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT is measured between VIH and VIL. 4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied. 5. t RHZ (max), tCHZ (max), tOFF1 (max), tOFF2 (max), tSHZ (max) and tSLZ (min) are defined as the time at which the output acheives the open circuit condition (VOH - 100 mV, VOL + 100 mV). This parameter is sampled and not 100% tested. 6. Assume that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 1 TTL loads and 50 pF. 8. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tCAC . 9. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tAA . 10. If either tRCH or tRRH is satisfied, operation is guaranteed. (HM538253) If both tRCH and t RRH are satisfied, operation is guaranteed, (HM538254) 11. When t WCS tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 12. These parameters are specified by the later falling edge of CAS or WE. 13. Either t CDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or OE prior to applying data to the device when output buffer is on. (HM538253B) Either t CDD (min), tODD (min) or tRDD (min) must be satisfied because the output buffer must be turned off by CAS, OE or RAS prior to applying data to the device when output buffer is on. (HM538254B) 14. When t AWD tAWD (min) and tCWD tCWD (min) in read-modify-write cycle, the data of the selected address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be satisfied because output buffer must be turned off by OE prior to applying data to the device. 15. Measured with a load circuit equivalent to 1 TTL loads and 30 pF. 16. After power-up, pause for 100 s or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. Hitachi recommends that least 8 initialization cycle is CBRR for internal register reset. 17. When t SHZ and t SLZ are measured in the same V CC and Ta condition and tr and tf of SE are less than 5 ns, t SHZ < tSLZ + 5 ns. 18. After power-up, QSF output may be High-Z, so 1SC cycle is needed to be Low-Z it. 19. DSF 2 pin is open pin, but Hitachi recommends it is fixed low in all operation for the addition mode in future. 31 HM538253B/HM538254B Series 20. XXX: H or L (H : VIH (min) V IN V IH (max), L : VIL (min) V IN V IL (max) ///////: Invalid Dout Timing Waveforms*20 Read Cycle (HM538253B) t RC t RAS RAS t CSH t RCD CAS t ASR Address Row t RAD t RAH t ASC Column t RCS t CAC t AA t RAC t DZC t DZO t DTS DT/OE t FSR DSF1 t RFH t FSC t CFH t DTH t OAC t OFF1 Valid Dout t OFF2 t RSH t CAS t RAL t CAH t RRH t CAL t CRP t RP t RCH t CDD WE I/O (Output) I/O (Input) 32 HM538253B/HM538254B Series Fast Page Mode Read Cycle (HM538253B) t RC t RASP RAS t CSH t CAS t RCD t RAD t ASR Address t RAH t ASC Row t CAL t CAH t PC t CP t CAS t CAL t CAH Column t RCS t RCH t AA t ACP t CAC t DZC t OAC t OFF1 Valid Dout t RP t RSH t CAS t CP t RAL t ASC t CRP CAS t ASC t CAL t CAH Column t RCS t AA t ACP t CAC Valid Dout Column t RCS t RCH t RAC t OFF1 t AA t CAC t DZC t CDD t OAC t OFF2 Valid Dout t RRH t RCH WE t OFF1 I/O (Output) t CDD t OFF2 t DZC t OAC t CDD I/O (Input) t DTS DT/OE t FSR DSF1 t DZO t DTH t RFH t FSC t CFH t FSC t CFH t FSC t CFH 33 HM538253B/HM538254B Series Write Cycle Table 3 below applies to early write, delayed write, page mode write, and read-modify write. Table 3 Write Cycle State RAS DSF1 Menu RWM BWM RW BW LMR*4 LCR*4 Cycle Write mask (new/old) Write DQs to I/Os Write mask (new/old) Block write Normal write (no mask) Block write (no mask) Load write mask resister Load color resister WE Low Mode New mask mode Persistent mask mode High No mask W1 0 0 0 0 1 1 CAS DSF1 W2 0 1 0 1 0 1 I/O data/RAS Mask H or L (mask register used) H or L RAS WE W3 0 0 1 1 1 1 RAS I/O W4 Write mask *1 CAS I/O W5 Valid data Column mask*2 Valid data Column mask*2 Write mask data*3 Color data Write mask*2 Don't care*1 Don't care *2 Don't care Don't care Notes: 1. I/O Mask data (In new mask mode) Low: Mask High: Non mask In persistent mask mode, I/O H or L 2. Reference Figure 2 use of block write. 3. I/O write mask data Low: Mask High: Non mask 4. Column Address: H or L 34 HM538253B/HM538254B Series Early Write Cycle t RC t RAS RAS t CSH t RCD CAS Address t ASR Row t WS WE I/O (Output) I/O (Input) DT/OE t FSR DSF1 W1 t RFH t FSC W2 t CFH W3 High-Z t MS W4 t DTS t DTH t MH t DS W5 t DH t WH t RAH t ASC Column t WCS t WCH t RSH t CAS t CAH t CRP t RP WI to W5: See write cycle state table for the logic states. 35 HM538253B/HM538254B Series Delayed Write Cycle t RC t RAS RAS t RCD CAS Address t ASR t RAH t ASC Column t RWL t WP t CWL t CSH t RSH t CAS t CAH t RP t CRP Row t WS t WH W3 WE I/O (Output) I/O (Input) t DTS DT/OE DSF1 t FSR t MS W4 t MH t DZC t DS t DH W5 t DTH t RFH W1 t OFF2 t ODD t FSC W2 t CFH t OEH WI to W5: See write cycle state table for the logic states. Fast/Hyper Page Mode Write Cycle (Early Write) t RC t RASP RAS t CSH t RCD CAS Address t ASR t RAH t ASC t CAS t CP t PC t CAS t CP t RSH t CAS t CAH Column t WCS t WCH t CRP t RP t CAH t ASC Column t CAH t ASC Row Column t WS t WH t WCS t WCH W3 t WCS t WCH WE I/O (Output) I/O (Input) t DTS DT/OE t FSR DSF1 t MS High-Z t MH W4 t DTH t RFH t FSC W1 W2 t CFH t FSC W2 t CFH t FSC W2 t CFH t DS t DH W5 t DS t DH W5 t DS t DH W5 WI to W5: See write cycle state table for the logic states. 36 HM538253B/HM538254B Series Fast/Hyper Page Mode Write Cycle (Delayed Write) t RC t RASP RAS t CSH t RCD CAS Address t ASR t RAH t ASC Row t WS WE I/O (Output) I/O (Input) t DTS DT/OE t FSR DSF1 t RFH t FSC W1 t CFH t FSC t CFH W2 t FSC t CFH t MS t WH W3 High-Z t MH W4 t DS t DH W5 t DS t DH W5 t DS t DH W5 t OEH Column t CWL t WP t CAS t CAH t CP t ASC Column t CWL t WP t PC t CAS t CAH t CP t RSH t CAS t CAH t RWL t WP t CRP t RP t ASC Column t CWL W2 W2 WI to W5: See write cycle state table for the logic states. Read-Modify-Write Cycle t RWC t RWS RAS t RCD CAS t RAD t ASR Address t WS WE I/O (Output) I/O (Input) DT/OE t FSR DSF1 W1 t RFH t FSC W2 t CFH t RAH t ASC t CAH t AWD t CWD t CAC t AA t RAC Valid Dout t MS t MH W4 t DTS t DTH t DZC t DZO t OAC t OFF2 t ODD t DS t DH W5 t OEH t RWL t CWL t WP t CRP t RP Row t WH W3 Column tRCS WI to W5: See write cycle state table for the logic states. 37 HM538253B/HM538254B Series RAS-Only Refresh Cycle (HM538253B) t RC t RAS RAS CAS Address t OFF1 I/O (Output) t CDD I/O (Input) t OFF2 t ODD t DTS DT/OE t FSR DSF1 t RFH t DTH t CRP t ASR t RAH t RPC t RP Row WE : H or L CAS-Before-RAS Refresh Cycle (CBRN) (HM538253B) t RC t RP RAS CAS Address t WS WE t OFF1 I/O (Output) DT/OE t FSR DSF1 t RFH High-Z t WH t RPC t CP t RAS t RP t CSR t CSR t CHR t RPC Inhibit Falling Transition SC : H or L 38 HM538253B/HM538254B Series Hidden Refresh Cycle (HM538253B) t RC t RAS RAS t RCD CAS t ASR Address Row t RSH t CHR t CRP t RP t RAS t RC t RP t RAD t RAL t RAH t ASC t CAH Column t RCS t CAC t AA t RAC t OFF1 Valid Dout t DZC t DZO t DTH t RFH t FSR t RFH t OAC t OFF2 t WH t RRH t WS WE I/O (Output) I/O (Input) t DTS DT/OE t FSR t FSC t CFH DSF1 CAS-Before-RAS Set Cycle (CBRS) t RC t RP RAS t RPC CAS t ASR *1 Address (A2-A7) WE I/O (Output) I/O (Input) DT/OE t FSR DSF1 Note: A0, A1, A8: H or L SC: H or L t RFH High-Z t RAH Stop Address t WS t WH t CSR t CHR Inhibit falling transition t CRP t RAS t RP 39 HM538253B/HM538254B Series CAS-Before-RAS Reset Cycle (CBRR) t RC t RP RAS t RPC CAS Address t WS WE I/O (Output) I/O (Input) DT/OE t FSR DSF1 t STS SC Bi*1 t RST Bj-2 Bj-1 Bj*1 t RFH High-Z t WH t CSR t CHR Inhibit falling transition t RAS t RP t CRP Notes: 1. Bi, Bj initiate the boundary addresses. When a CBRR is executed for stopping column operation reset and split transfer operation, it needs to satisfy tSTS (min) and tRST (min) between RAS falling and SC rising. 2. Ym, Yn are the SAM start address in before SRT/MSWT. 40 HM538253B/HM538254B Series Flash Write Cycle (HM538253B) t RC t RAS RAS t CRP CAS Address t ASR Row t WS WE t OFF1 I/O (Output) I/O (Input) DT/OE DSF1 t OFF2 t CDD High-Z t ODD t DTS t MS t MH t WH t RCD t RAH t RP Mask Data t DTH t FSR t RFH 41 HM538253B/HM538254B Series Register Read Cycle (Mask data, Color data) (HM538253B) t RC t RAS RAS t RCD CAS Address t ASR t RAH t CSH t CAS t RSH t RP t CRP Row t WS t WH t RCS t CAC t RRH t RCH WE t RAC I/O (Output) I/O (Input) t DTS DT/OE DSF1 t FSR t DZC t CDD t OFF1 Valid Out t OFF2 Note: 1. State of DFS1 at falling edge of CAS State Accessed data 0 1 Color data (LCR) t DZO t DTH t RFH t FSC *1 t OAC t ODD t CFH Mask data (LMR) 42 HM538253B/HM538254B Series Read Transfer Cycle 1 tRC t RAS RAS t CSH t RCD CAS t ASR Address Row t WS WE I/O (Output) t DTS DT/OE t FSR DSF1 t SCC SC t SCC t SDD t SCA t SOH Valid Sout t SCA t SOH Valid Sout t SCA t SOH Valid Sout High-Z t DQD t DQH QSF SAM Address MSB t SCC t SDH t SCC t SC t SCA t SOH Valid Sout Previous Row t SCP t SOH Valid Sout New Row t RFH t RDH High-Z t CDH t ADH t DTP t DRD t WH t RAD t RAH t RAL t ASC t CAH SAM Start Address t RP t CRP t RSH t CAS SI/O (Output) SI/O (Input) 43 HM538253B/HM538254B Series Read Transfer Cycle 2 t RC t RAS RAS t CSH t RCD CAS t ASR Address t WS WE I/O (Output) DT/OE t FSR DSF1 t RP t CRP t RSH t CAS t RAL t RAD t RAH t ASC t CAH Row t WH SAM Start Address High-Z t DTS t DTH t DTP t DRD t RFH t SRS t SC SC t SAH Inhibit Rising Transition t SCH t SRH t SDH t SCP t SC t SCC t SCP t SCA t SOH Valid Sout t SCA SI/O (Output) SI/O (Input) t SIS t SIH t SZS Valid Sin t RQD t RQH QSF SAM Address MSB t CQD t CQH t DQH t DQD 44 HM538253B/HM538254B Series Masked Write Transfer Cycle t RC t RAS RAS t RCD CAS Address t ASR t RAH t ASC t CAH t CSH t CAS t RSH t RP t CRP Row t WS t WH SAM Start Address WE I/O (Output) DT/OE t FSR t RFH DSF1 t SRS t SC SC SI/O (Output) SI/O (Input) t SCA Valid t SOH t SRZ Valid High-Z t CQH t CQD Inhibit Rising Transition t SID t SIS t SIH Valid Sin High-Z t DTS t DTH t SRD t SCP t SCC t SC t SCP t SIS t SIH Valid Sin QSF I/O (Input) t RQD t RQH SAM Address MSB t MS t MH I/O Mask Data *1 Note: 1. I/O mask data (In new mask mode) Low: Mask High: Non mask I/O: H or L in persistent mask mode. 45 HM538253B/HM538254B Series Split Read Transfer Cycle (HM538253B) t RC t RAS t RP t CSH t CRP t RCD t RSH t CAS t CRP RAS CAS t ASR t RAD t RAH t ASC t CAH t RAL SAM Start Address Yi Address Row t WS t WH WE t OFF1 I/O (Output) t DTS t DTH High-Z DT/OE t FSR t RFH DSF1 t CST t AST t RST t SCC t STS t SC t SCP SC Bi *2 t SCA t SOH Valid Sout Ym*1 Ym + 1 t SCA t SOH Ym + 2 Bj - 2 Bj - 1 Bj *2 Yi SI/O (Output) SI/O (Input) Valid Sout Valid Sout Valid Sout Valid Sout Valid Sout High-Z t SQD t SQH t SQD t SQH QSF SAM Address MSB Notes: 1. Ym is the SAM start address in before SRT. 2. Bi, Bj initiate the boundary address. 3. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit. SAM start address can't set on the boundary address. 46 HM538253B/HM538254B Series Masked Split Write Transfer Cycle (HM538253B) t RC t RAS RAS t RCD CAS t ASR t RAH Address Row t WS tWH WE t OFF1 I/O (Output) t DTS t DTH DT/OE t FSR t RFH DSF1 t RST t STS SC SI/O (Output) t SIS t SIH SI/O (Input) Valid Sin Valid Sin Valid Sin t RP t CSH t RSH t CAS t ASC t CAH SAM Start Address Yi High-Z t AST t CST t SCC t SC t SCP Ym*1 Ym+1 Ym+2 Bj-2 Bj-1 Bj*2 Yi Bi*2 t SIS t SIH Valid Sin Valid Sin t SIS t SIH Valid Sin Valid Sin t SQD t SQH SAM Address MSB t CDD t MS t MH t SQD t SQH QSF I/O (Input) *3 I/O Mask Data Notes: 1. Ym is the SAM start address in before MSWT. 2. Bi, Bj initiate the boundary address. 3. I/O Mask data (In new mask mode) Low: Mask High: Non mask I/O: H or L in persistent mask mode. 4. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit. SAM start address can't set on the boundary address. 47 HM538253B/HM538254B Series Serial Read Cycle SE tSCC tSC SC tSCA tSOH Valid Sout tSCP tSC tSCC tSCP tSC tSEA tSCA tSLZ tSCC tSCP tSC tSCA tSOH Valid Sout Valid Sout tSHZ Valid Sout SI/O (Output) Serial Write Cycle tSWH SE tSCC tSC SC tSIS SI/O (Input) tSIH tSIS tSIH tSIS tSIH tSCP tSC tSCC tSCP tSC tSCC tSCP tSC tSWIS tSWIH tSWS Valid Sin Valid Sin Valid Sin Read Cycle (HM538254B) t RC t RAS RAS t CSH t RCD CAS t ASR Address Row t RAD t RAH t ASC Column t RCS t CAC t AA t RAC t DZC t DZO t DTS DT/OE t FSR DSF1 t RFH t FSC t CFH t DTH t OAC t RSH t CAS t RAL t CAH t RRH t CAL t CRP t RP t RCH t CDD t RHZ t CHZ WE I/O (Output) I/O (Input) Valid Dout t OFF2 t RDD t ODD 48 HM538253B/HM538254B Series Hyper Page Mode Read Cycle (HM538254B) t RC t RASP RAS t CSH t CAS t RCD t RAD t ASR Address t RAH t ASC Row t CAL t CAH t PC t CP t CAS t CAL t CAH Column t CP t RAL t ASC t CAL t CAH Column t RRH t AA t ACP t CAC Valid Dout Valid Dout t RP t RSH t CAS t CRP CAS t ASC Column t RCS t RAC t AA t CAC t DZC t RCH WE t AA t ACP t CAC Valid Dout t CHZ t RHZ t CDD t ODD I/O (Output) t OAC t DOH t DOH t RDD t OFF2 I/O (Input) t DTS DT/OE t FSR DSF1 t DZO t DTH t RFH t FSC t CFH t FSC t CFH t FSC t CFH RAS-Only Refresh Cycle (HM538254B) t RC t RAS RAS CAS Address t CHZ I/O (Output) t CDD I/O (Input) t OFF2 t ODD t DTS DT/OE t FSR DSF1 t RFH t DTH t CRP t ASR t RAH t RPC t RP Row WE : H or L 49 HM538253B/HM538254B Series CAS-Before-RAS Refresh Cycle (CBRN) (HM538254B) t RC t RP RAS CAS Address t WS WE t RHZ I/O (Output) DT/OE t FSR DSF1 SC : H or L t RFH t CHZ High-Z t WH t RPC t CP t RAS t RP t CSR t CSR t CHR t RPC Inhibit Falling Transition Hidden Refresh Cycle (HM538254B) t RC t RAS RAS t RCD CAS t ASR Address Row t RSH t CHR t CRP t RP t RAS t RC t RP t RAD t RAL t RAH t ASC t CAH Column t RCS t CAC t AA t RAC t CHZ t RHZ Valid Dout t DZC t DZO t DTH t RFH t FSR t RFH t OAC t OFF2 t WH t RRH t WS WE I/O (Output) I/O (Input) t DTS DT/OE t FSR t FSC t CFH DSF1 50 HM538253B/HM538254B Series Flash Write Cycle (HM538254B) t RC t RAS RAS t CRP CAS Address t ASR Row t WS WE t CHZ I/O (Output) I/O (Input) DT/OE DSF1 t OFF2 t CDD High-Z t ODD t DTS t MS t MH t WH t RCD t RAH t RP Mask Data t DTH t FSR t RFH 51 HM538253B/HM538254B Series Register Read Cycle (Mask data, Color data) (HM538254B) t RC t RAS RAS t RCD CAS Address t ASR t RAH t CSH t CAS t RSH t RP t CRP Row t WS t WH t RCS t CAC t RHZ Valid Out t OAC t RRH t CDD t CHZ t OFF2 t ODD t RDD t RCH WE t RAC I/O (Output) I/O (Input) t DTS DT/OE DSF1 t FSR t DZC Note: 1. State of DFS1 at falling edge of CAS State Accessed data 0 1 Color data (LCR) t DZO t DTH t RFH t FSC *1 t CFH Mask data (LMR) 52 HM538253B/HM538254B Series Split Read Transfer Cycle (HM538254B) t RC t RAS t RP t CSH t CRP t RCD t RSH t CAS t CRP RAS CAS t ASR t RAD t RAH t ASC t CAH t RAL SAM Start Address Yi Address Row t WS t WH WE t CHZ I/O (Output) t DTS t DTH High-Z DT/OE t FSR t RFH DSF1 t CST t AST t RST t SCC t STS t SC t SCP SC Bi *2 t SCA t SOH Valid Sout Ym*1 Ym + 1 t SCA t SOH Ym + 2 Bj - 2 Bj - 1 Bj *2 Yi SI/O (Output) SI/O (Input) Valid Sout Valid Sout Valid Sout Valid Sout Valid Sout High-Z t SQD t SQH t SQD t SQH QSF SAM Address MSB Notes: 1. Ym is the SAM start address in before SRT. 2. Bi, Bj initiate the boundary address. 3. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit. SAM start address can't on the boundary address. 53 HM538253B/HM538254B Series Masked Split Write Transfer Cycle (HM538254B) t RC t RAS RAS t RCD CAS t ASR t RAH Address Row t WS tWH WE t CHZ I/O (Output) t DTS t DTH DT/OE t FSR t RFH DSF1 t RST t STS SC SI/O (Output) t SIS SI/O (Input) Valid Sin t RP t CSH t RSH t CAS t ASC t CAH SAM Start Address Yi High-Z t AST t CST t SCC t SC t SCP Ym*1 Ym+1 Ym+2 Bj-2 Bj-1 Bj*2 Yi Bi*2 t SIH Valid Sin Invalid Dout t SIS t SIH Valid Sin Valid Sin Valid Sin t SIS t SIH Valid Sin Valid Sin t SQD t SQH t SQD t SQH SAM Address MSB QSF t CDD t MS I/O (Input) t MH *3 I/O Mask Data Notes: 1. Ym is the SAM start address in before MSWT. 2. Bi, Bj initiate the boundary address. 3. I/O Mask data (In new mask mode) Low: Mask High: Non mask I/O: H or L in persistent mask mode. 4. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit. SAM start address can't set or the boundary address. 54 HM538253B/HM538254B Series Package Dimensions HM538253BJ/HM538254BJ Series (CP-40D) 25.80 26.16 Max 40 21 10.16 0.13 11.18 0.13 Unit: mm 0.74 3.50 0.26 1 20 1.30 Max 0.43 0.10 1.27 0.10 0.80 9.40 0.25 HM638253BTT/HM538254BTT Series (TTP-44/40DA) 18.41 18.81 Max 35 32 0.31 2.30 + 0.14 - +0.25 -0.17 Unit: mm 44 23 1 10 13 0.80 0.21 M 1.005 Max 2.40 0.10 22 0.30 0.10 10.16 11.76 0.20 0 - 5 0.80 1.20 Max 0.17 0.05 0.13 0.05 0.50 0.10 55 |
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